Element value comparison in memory
AssigneeMicron Technology, Inc.
InventorSanjay Tiwari
Life of this patent
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Abstract
The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.
Claims20
A system, comprising:
- a host configured to generate instructions;
- a memory device coupled to the host and comprising an array of memory cells configured to store a plurality of elements;
- and
- control circuitry configured to execute instructions from the host by causing logical operations to be performed on a pair of elements stored in memory cells corresponding to a same column of the array to compare values of respective elements of the pair of elements.
A method for performing an element comparison, comprising:
- generating instructions on a host coupled to a memory device comprising an array of memory cells configured to store a plurality of elements;
- and
- executing the instructions using control circuitry of the memory device, wherein executing the instructions comprises:
- comparing, by using sensing circuitry coupled to a column of the array, values of respective elements of a pair of elements stored in memory cells corresponding to the column of the array;
- and
- wherein the comparing comprises causing performance of logical operations on the pair of elements without transferring the elements to the host.
A system, comprising:
- a host configured to generate instructions;
- a memory device coupled to the host and comprising an array of memory cells configured to store a plurality of elements;
- and
- wherein the memory device is configured to execute the instructions to:
- perform, using sensing circuitry coupled to the array, a plurality of greater vector determination operations, in parallel, by comparing a plurality of first elements stored as bit-vectors in a first group of memory cells to a plurality of second elements stored as bit-vectors in a second group of memory cells;
- and
- cause a plurality of results of the respective plurality of greater vector determination operations to be stored in the array.
Dependencies are inferred from the claim text.