Memory read circuit with n type and p type pre-charge
AssigneeIntel Corporation
InventorsRajiv KUMAR, Kuan Cheng TANG
Life of this patent
Estimating the term…
Abstract
A memory is described. The memory includes a storage cell. The memory also includes a read bit line coupled to the storage cell. The memory also includes at least one N type pre charge transistor coupled between the read bit line and a power supply node. The at least one N type pre-charge transistor is to pre-charge the read bit line. The memory also includes at least one P type pre charge transistor that is also coupled between the read bit line and the power supply node. The at least one P type pre-charge transistor is to pre-charge the read bit line with the at least one N type transistor.
Claims20
A memory, comprising:
- a storage cell;
- a read bit line coupled to the storage cell;
- at least one N type pre charge transistor coupled between the read bit line and a power supply node, the at least one N type pre-charge transistor to pre-charge the read bit line;
- at least one P type pre charge transistor also coupled between the read bit line and the power supply node, the at least one P type pre-charge transistor to pre-charge the read bit line with the at least one N type transistors
- wherein, the read bit line is coupled between the at least one N type pre charge transistor and the at least one P type pre charge transistor.
A computing system, comprising:
- a plurality of processing cores;
- a system memory controller;
- a system memory;
- an SRAM memory, the SRAM memory comprising:
- a storage cell;
- a read bit line coupled to the storage cell;
- at least one N type pre charge transistor coupled between the read bit line and a power supply node, the at least one N type pre-charge transistor to pre-charge the read bit line;
- at least one P type pre charge transistor also coupled between the read bit line and the power supply node, the at least one P type pre-charge transistor to pre-charge the read bit line with the at least one N type transistors
- wherein, the read bit line is coupled between the at least one N type pre charge transistor and the at least one P type pre charge transistor.
A method of reading a memory storage cell, comprising:
- turning on both P type and N type pre charge transistors that are coupled to a read bit line, the read bit line coupled to the storage cell and coupled between the P type and N type pre charge transistors, the turning on of the P type and N type transistors to pre charge the read bit line;
- sensing a voltage level of the read bit line after the turning on of the P type and N type pre charge transistors to determine a value stored by the storage cell.
Dependencies are inferred from the claim text.