Gate driving circuit and display device using the same
AssigneeLG Display Co., Ltd.
InventorsYeonkyung KIM, Taewoong MOON, Junghyun LEE
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a gate driving circuit and a display device using the circuit. A gate driving circuit according to an aspect of the present disclosure comprises a Q node controller, a QB node controller, and an output unit generating a pulse-type output signal by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node, and the QB node controller controls the voltage of the QB node in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.
Claims19
A gate driving circuit, comprising:
- a Q node controller controlling a voltage of Q node;
- a QB node controller controlling a voltage of QB node;
- and
- an output unit generating a pulse-type output signal synchronized with a part of a 1st clock by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node,
- wherein the voltage of the QB node is controlled in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.
A display device, comprising:
- a display panel including data lines, gate lines, and pixels defined by the data lines and the gate lines;
- a data driving circuit providing data signals to the data lines of the display panel;
- a gate driving circuit providing gate pulses synchronized with the data signals to the gate lines of the display panel and including a plurality of stages connected in a cascade manner;
- and
- a timing controller controlling timings of the data driving circuit and the gate driving circuit,
- wherein each stage includes
- a Q node controller controlling a voltage of Q node;
- a QB node controller controlling a voltage of QB node;
- and
- an output unit generating a pulse-type output signal synchronized with a part of a 1st clock by controlling charging and discharging of an output terminal according to the voltages of the Q node and the QB node,
- wherein the voltage of the QB node is controlled in an alternating manner during a non-scan period in which the Q node controller outputs a low level voltage for the Q node.
Dependencies are inferred from the claim text.