Gate driver and flat panel display device including the same
AssigneeLG Display Co., Ltd.
InventorsSeok NOH, Hae-Jin PARK, Ki-Min SON
Life of this patent
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Abstract
Disclosed herein are a gate driver capable of implementing a narrow bezel by deleting dummy gate-in-panels (GIPs) and a flat panel display device including the same. The gate driver includes gate-in-panels (GIPs) equal in number to a plurality of gate lines in order to sequentially supply scan pulses to the plurality of gate lines. A k-th GIP is enabled by a carry pulse from a GIP of a (k−a)-th stage and is disabled by a carry pulse output from a GIP of a (k+b)-th stage (a and b are natural numbers), first a GIPs are enabled by a gate start signal output from a timing controller, and last b GIPs are disabled by a reset signal output from the timing controller.
Claims13
A gate driver, comprising:
- a plurality of gate in panel (GIP) stages configured to sequentially supply scan pulses to a plurality of gate lines of a display panel, the plurality of GIP stages being equal in number to the plurality of gate lines, the plurality of GIP stages including:
- n first GIP stages which are enabled by a gate start signal output from a timing controller;
- m last GIP stages which are disabled by a reset signal output from the timing controller;
- and
- at least one GIP stage between the n first GIP stages and the m last GIP stages, the at least one GIP stage including a k-th GIP stage which is enabled by a carry pulse output from a (k−n)-th GIP stage and is disabled by a carry pulse output from a (k+m)-th GIP stage, wherein n, m, and k are natural numbers.
A flat panel display device, comprising:
- a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels formed in a matrix to supply data voltages to the plurality of data lines in response to scan pulses supplied to the gate lines to display an image;
- a gate driver for sequentially supplying the scan pulses to the plurality of gate lines;
- a data driver for supplying the data voltages to the plurality of data lines;
- and
- a timing controller for respectively supplying a plurality of gate control signals and a plurality of data control signals to the gate driver and the data driver,
- wherein the gate driver includes a plurality of gate in panel (GIP) stages equal in number to the plurality of gate lines, and
- wherein a k-th GIP stage is enabled by a carry pulse output from a (k−n)-th GIP stage and is disabled by a carry pulse output from a (k+m)-th GIP stage (n and m are natural numbers), a first set of n GIP stages are enabled by a gate start signal output from the timing controller, and a last set of m GIP stages are disabled by a reset signal output from the timing controller.
Dependencies are inferred from the claim text.