Tile aware sector cache for graphics
AssigneeIntel Corporation
InventorsAltug Koker, Aditya Navale
Life of this patent
Estimating the term…
Abstract
Methods and apparatus relating to tile-aware sector cache for graphics are described. One embodiment enables a sector cache implementation (e.g., in graphics implementations) to reduce the size of the tag space. The reduction in tag space, in turn, reduces power consumption, (e.g., via reduced ways). Moreover, cache efficiency is maintained by keeping the sector utilization at a high rate in one or more embodiments. Other embodiments are also disclosed and claimed.
Claims25
An apparatus comprising:
- a sector cache to store data, wherein the sector cache comprises an address tag space and a plurality of sectors, wherein the address tag space comprises a plurality of address tags, wherein each of the plurality of address tags is associated with a sector from of the plurality of sectors;
- and
- logic, at least a portion of which is in hardware, to configure the tag space of the sector cache to provide spatial locality based at least in part on patterns present in the data stored in the sector cache.
A method comprising:
- storing data in a sector cache, wherein the sector cache comprises an address tag space and a plurality of sectors, wherein the address tag space comprises a plurality of address tags, wherein each of the plurality of address tags is associated with a sector from of the plurality of sectors;
- and
- configuring, at logic, the tag space of the sector cache to provide spatial locality based at least in part on patterns present in the data stored in the sector cache.
One or more computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
- store data in a sector cache, wherein the sector cache comprises an address tag space and a plurality of sectors, wherein the address tag space comprises a plurality of address tags, wherein each of the plurality of address tags is associated with a sector from of the plurality of sectors;
- and
- configure, at logic, the tag space of the sector cache to provide spatial locality based at least in part on patterns present in the data stored in the sector cache.
A computing system comprising:
- a processor having one or more processor cores;
- memory, coupled to the processor, to store one or more bits of data;
- and
- a sector cache to store data, wherein the sector cache comprises an address tag space and a plurality of sectors, wherein the address tag space comprises a plurality of address tags, wherein each of the plurality of address tags is associated with a sector from of the plurality of sectors;
- and
- logic, at least a portion of which is in hardware, to configure the tag space of the sector cache to provide spatial locality based at least in part on patterns present in the data stored in the sector cache.
Dependencies are inferred from the claim text.