Using programmable switching chips as artificial neural networks engines

A system for executing a binarized neural network (BNN) using a switching chip, the BNN being provided as a binarized form of an artificial neural network application, the system comprising:

• a parser of the switching chip configured to encode an input vector of the BNN in a packet header;
• a plurality of stages of the switching chip having match-action tables (MATs) configured to execute, on the input vector encoded in the packet header, one or more of the operations including XNOR, bit counting, and sign operations such that the plurality of MATs are configured to:
• implement, in a first stage, a bitwise XNOR operation between the input vector encoded in the packet header and a weights matrix of the neural network to produce a plurality of first stage vectors,
• implement, in one or more second stages, an algorithm for counting a number of bits set to 1 in the plurality of first stage vectors to produce a plurality of second stage vectors, and
• implement, in a last stage, a sign function operation on the plurality of second stage vectors;
• and
• a deparser configured to construct a new packet header using the result of the sign operation.