Integrated circuit, system for and method of forming an integrated circuit

A method of fabricating an integrated circuit, the method comprising:

• generating a set of gate layout patterns, each gate layout pattern of the set of gate layout patterns being separated from one another in a first direction, the set of gate layout patterns being located at a first layout level and extending in a second direction different from the first direction;
• generating a first conductive structure layout pattern extending in the first direction, overlapping the set of gate layout patterns and being located at a second layout level different from the first layout level;
• generating a first set of via layout patterns between the set of gate layout patterns and the first conductive structure layout pattern, each via layout pattern of the first set of via layout patterns being located where the first conductive structure layout pattern overlaps each gate layout pattern of the set of gate layout patterns;
• generating a first set of conductive structure layout patterns extending in the second direction, overlapping the first conductive structure layout pattern, and being located at a third layout level, each conductive structure layout pattern of the first set of conductive structure layout patterns being separated from each other in the first direction and being positioned between a pair of gate layout patterns of the set of gate layout patterns;
• and
• generating a second set of via layout patterns between the first set of conductive structure layout patterns and the first conductive structure layout pattern, each via layout pattern of the second set of via layout patterns being located where the first set of conductive structure layout patterns overlaps the first conductive structure layout pattern;
• wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor;
• and
• manufacturing the integrated circuit based on at least one of the above layout patterns of the integrated circuit.

A method of fabricating an integrated circuit, the method comprising:

• placing a set of gate layout patterns on a first layout level, each gate layout pattern of the set of gate layout patterns being separated from one another in a first direction, the set of gate layout patterns extending in a second direction different from the first direction;
• placing a first conductive structure layout pattern on a second layout level different from the first layout level, the first conductive structure layout pattern extending in the first direction and overlapping the set of gate layout patterns;
• placing a first set of via layout patterns between the set of gate layout patterns and the first conductive structure layout pattern, each via layout pattern of the first set of via layout patterns being located where the first conductive structure layout pattern overlaps each gate layout pattern of the set of gate layout patterns;
• generating a second conductive structure layout pattern extending in the second direction, overlapping the first conductive structure layout pattern, and being located at a third layout level different from the first layout level and the second layout level, the second conductive structure layout pattern being positioned between a first pair of gate layout patterns of the set of gate layout patterns;
• and
• generating a third conductive structure layout pattern extending in the second direction, overlapping the first conductive structure layout pattern, and being located at the third layout level, the third conductive structure layout pattern being positioned between a second pair of gate layout patterns of the set of gate layout patterns, the third conductive structure layout pattern being separated from the second conductive structure layout pattern in the first direction;
• wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor;
• and
• manufacturing the integrated circuit based on at least one of the above layout patterns of the integrated circuit.