System and method for anti reverse engineering for analog integrated circuit
AssigneeIpgreat Incorporated
InventorsYUAN-JU CHAO, TA-SHUN CHU
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Abstract
Systems and methods of restraining reverse engineering process for analog integrated circuit use techniques of adding dummy devices, device fragmentation, increasing bus width, employing different layouts for the same circuit element and mixing different types of passive devices increase complexity and makes the layout floorplan more difficult to be extracted for the reverse engineering. The system adds dummy devices and ensures the extra devices and capacitance do not affect the target circuit performance.
Claims20
A method for designing an integrated circuit (IC), comprising:
- adding anti-reverse engineering for the IC by expanding complexity of one or more circuits or disguising a selected circuit;
- and
- rendering a layout of the IC with the anti-reverse engineering design.
A system to design an integrated circuit (IC), comprising:
- a processor to receive an IC design with one or more circuits thereon;
- code for adding anti-reverse engineering for the IC by expanding a complexity of one or more circuits or disguising a selected circuit;
- and
- code for rendering a layout of the IC with the anti-reverse engineering design.
An integrated circuit, comprising:
- a plurality of functioning circuits on a substrate;
- a disguised circuit on the substrate or one or more complexity adding circuits on the substrate to foil piracy,
- wherein the disguised circuit or the complexity adding circuit meets a predetermined performance with added devices and associated extra capacitance of the dummy devices.
Dependencies are inferred from the claim text.