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US 2019/0102497 A1Published application
Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks
AssigneeIntel Corporation
InventorsMahesh A. IYER, Vasudeva M. KAMATH
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Abstract
A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.
Claims21
A method for designing a system on a target device, comprising:
- performing register retiming on an original design to generate a retimed design of the system;
- identifying compare points in the original design and the retimed design where signal values reflect initial states of one or more flip-flops;
- performing bounded sequential logic simulation within a time frame;
- and
- determining whether changed flip-flops in the retimed design have initial states that are correct by comparing signal values at the compare points from the bounded sequential logic simulation.
2 more elements
A method for designing a system on a target device, comprising:
- performing register retiming on an initial design to generate a retimed design;
- determining whether the retimed design is structurally correct;
- determining whether unchanged registers in the retimed design have initial states that are correct in response to determining whether the retimed design is structurally correct;
- and
- determining whether changed registers in the retimed design have initial states that are correct in response to determining that the unchanged registers in the retimed design have initial states that are correct.
2 more elements
A system designer, comprising:
- a register retiming unit that performs register retiming on an original design for the system to generate a retimed design;
- and
- a verification unit that identifies unchanged flip-flops and verifies initial state equivalence of unchanged flip-flops between the original design and the retimed design, wherein at least one of the register retiming unit and the verification unit is implemented by a processor.
Dependencies are inferred from the claim text.