Generating a template-driven schematic from a netlist of electronic circuits

A computer system, comprising:

• a memory;
• and
• a processing device communicatively coupled to the memory, wherein the memory stores instructions that when executed by the processing device cause the processing device to:
• receive an indication to import, a simulation exchange format (SEF) file defining an electronic design, to a first Electronic Design Automation (EDA) tool executing on the computer system, the SEF file comprising information sufficient to recreate the placement and routing of components in the electronic design;
• process the SEF file to identify component objects and associate model names to the identified component objects;
• process the SEF file to map components to a symbol and obtain location, rotation, and mirroring information pertaining to the symbol;
• process the SEF file to place components and route wires between components based on at least one constraint;
• and
• present a schematic view of the electronic design in the first EDA tool.

A non-transitory computer readable medium comprising instructions stored thereon that when executed by a processing device cause the processing device to:

• receive an indication to export information pertaining to a first electronic design from a first Electronic Design Automation (EDA) tool executing on the computer system, the indication to export comprising information to request export in a common file format;
• exporting information describing the first electronic design from the first EDA tool;
• and
• store the information in a first simulation exchange format (SEF) file describing the first electronic design based on the common file format, wherein the common file format includes information sufficient to recreate the placement and routing of components in the first electronic design.

The non-transitory computer readable medium of claim 18, further comprising instructions to cause the processing device to:

• receive an indication to import, a second simulation exchange format (SEF) file defining a second electronic design, to the first Electronic Design Automation (EDA) tool, the second SEF file comprising information sufficient to recreate the placement and routing of components in the second electronic design;
• process the second SEF file to identify component objects and associate model names to the identified component objects;
• process the second SEF file to map components to a symbol and obtain location, rotation, and mirroring information pertaining to the symbol;
• process the second SEF file to place components and route wires between components based on at least one constraint;
• and
• present a schematic view of the second electronic design in the first EDA tool.