US 2019/0102358 A1 · RESISTIVE RANDOM ACCESS MEMORY MATRIX MULTIPLICATION STRUCTURES AND METHODS

Abstract

Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.

Claims20

Dependent claims

A non-volatile memory logic system, comprising:

bit lines and at a set of wordlines;
a set of resistive switching memory circuits at respective intersections between the bit lines and the set of wordlines, wherein resistive switching memory cells within the set of resistive switching memory circuits are programmed with respective bit values corresponding to a first data matrix, and wherein a second data matrix, represented by a set of electrical currents input onto wordlines of the set of wordlines, is provided to the non-volatile memory logic system as a system input, and
wherein, in response to an input of the second data matrix and a programming of the resistive switching memory cells to the first data matrix, the non-volatile memory logic system generates an output on the bit lines.

Dependencies are inferred from the claim text.

Facts

Application

16/144,765Filed 27 Sep 2018

Priority

29 Sep 2017

Published

4 Apr 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification19 codes

G11C 13/0069
Auxiliary circuits: writing or programming circuits or methods
G06F 17/16
Complex mathematical operations: matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 8/12
Arrangements for selecting an address in a digital store: group selection circuits, e.g. for memory block selection, chip selection, array selection

Resistive random access memory matrix multiplication structures and methods

Life of this patent

Resistive random access memory matrix multiplication structures and methods

Life of this patent

Abstract

Claims20