Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator

A method comprising:

• decoding an instruction with a decoder of a core of a processor into a decoded instruction;
• executing the decoded instruction with an execution unit of the core of the processor to perform a first operation;
• receiving an input of a dataflow graph comprising a plurality of nodes forming a loop construct;
• overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements and at least one dataflow operator controlled by a sequencer dataflow operator of the plurality of processing elements;
• and
• performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements and the sequencer dataflow operator generating control signals for the at least one dataflow operator in the plurality of processing elements.

A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

• decoding an instruction with a decoder of a core of a processor into a decoded instruction;
• executing the decoded instruction with an execution unit of the core of the processor to perform a first operation;
• receiving an input of a dataflow graph comprising a plurality of nodes forming a loop construct;
• overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements and at least one dataflow operator controlled by a sequencer dataflow operator of the plurality of processing elements;
• and
• performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements and the sequencer dataflow operator generating control signals for the at least one dataflow operator in the plurality of processing elements.