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US 2019/0102314 A1Published application
Tag cache adaptive power gating
AssigneeIntel Corporation
InventorsZhe Wang, Zeshan Chishti, Nagi Aboulenein, Zvika Greenfield
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Abstract
An embodiment of a semiconductor package apparatus may include technology to determine a workload characteristic for a tag cache, and adjust a power parameter for the tag cache based on the workload characteristic. Other embodiments are disclosed and claimed.
Claims24
An electronic processing system, comprising:
- a processor;
- memory communicatively coupled to the processor;
- a tag cache communicatively coupled to the processor;
- and
- logic communicatively coupled to the processor to:
- determine a workload characteristic for the tag cache, and
- adjust a power parameter for the tag cache based on the workload characteristic.
4 more elements
A semiconductor package apparatus, comprising:
- a substrate;
- and
- logic coupled to the substrate, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the substrate to:
- determine a workload characteristic for a tag cache, and
- adjust a power parameter for the tag cache based on the workload characteristic.
2 more elements
A method of controlling a memory, comprising:
- determining workload characteristic for a tag cache;
- and
- adjusting a power parameter for the tag cache based on the workload characteristic.
At least one computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
- determine a workload characteristic for a tag cache;
- and
- adjust a power parameter for the tag cache based on the workload characteristic.
Dependencies are inferred from the claim text.