Accelerator fabric
AssigneeIntel Corporation
InventorsRitu Gupta, Aravindh V. Anantaraman, Stephen R. Van Doren, Ashok Jagannathan
Life of this patent
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Abstract
A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.
Claims25
A fabric controller to provide a coherent accelerator fabric, comprising:
- a host interconnect to communicatively couple to a host device;
- a memory interconnect to communicatively couple to an accelerator memory;
- an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC);
- and
- an LLC controller configured to provide a bias check for memory access operations.
An accelerator apparatus, comprising:
- an accelerator, comprising a last-level cache (LLC);
- and
- a fabric controller to provide a coherent accelerator fabric, comprising:
- a host interconnect to communicatively couple the accelerator to a host device;
- a memory interconnect to communicatively couple the accelerator and the host device to an accelerator memory;
- an accelerator interconnect to communicatively couple the accelerator fabric to the LLC;
- and
- an LLC controller configured to provide a bias check for memory access operations.
One or more tangible, non-transitory computer-readable mediums having stored thereon instructions to provide a fabric controller, comprising instructions to:
- provision a host interconnect to communicatively couple to a host device;
- provision a memory interconnect to communicatively couple to an accelerator memory;
- provision an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC);
- and
- provision an LLC controller configured to provide a bias check for memory access operations.
Dependencies are inferred from the claim text.