US 2019/0102310 A1 · METHOD AND APPARATUS FOR CONTROL OF A TIERED MEMORY SYSTEM

Abstract

A method and apparatus for controlling data organization in a tiered memory system, where the system comprises a lower and higher bandwidth memories. Accesses to the tiered memory system by an action of a computing device in a first time interval are monitored to determine a first measure of bandwidth utilization, from which it is determined if the action is in a high bandwidth phase for which a first measure of bandwidth utilization is greater than an upper value. It is further determined, from confidence counters, if a monitored access is consistent with respect to the first instructions or with respect to a memory address of the access. Data associated with the access is moved from the lower bandwidth memory to the higher bandwidth memory when the action is in a high bandwidth phase, the access is consistent, and bandwidth utilization of the higher bandwidth memory is below a threshold.

Claims24

Dependent claims

A method for controlling data organization in a tiered memory system, the method comprising:

monitoring accesses to the tiered memory system by an action of a computing device in a first time interval to provide a first measure of bandwidth utilization of a first memory of the tiered memory system, the action due to execution of first instructions by the computing device;
determining when the action is in a high bandwidth phase for which a first measure of bandwidth utilization is greater than an upper value;
determining when an access of the monitored accesses is consistent with respect to the first instructions or with respect to a memory address of the access;
and
writing data associated with the access of the first memory to a second memory of the tiered memory system when the action is in a high bandwidth phase and the access is consistent,
where the second memory has a higher bandwidth than the first memory

3 more elements

An apparatus for organizing data storage in a tiered memory system comprising first and second memories, where the second memory has a higher bandwidth than the first memory, and where the apparatus comprises:

a one or more bandwidth utilization counters that update responsive to an access to the tiered memory system by a computing device, where the computing device executes a program of instructions in accordance with a program counter;
control logic that determines, from the one or more bandwidth utilization counters, when the computing device is in a high bandwidth phase;
and
a table of confidence counters that updates responsive to the access to the tiered memory system, where the table of confidence counters is indexed by a function of addresses accessed in the tiered memory or by a function of values of the program counter of the computing device, or by a function of the accessed address and the values of the program counters,
where the control logic identifies, from the table of confidence counters, when data stored at a first address in the first memory is repeatedly accessed while the computing device is in a high bandwidth phase, and
where the control logic causes the identified data at the first address in the first memory to be written to a second address in the second memory.

3 more elements

Dependencies are inferred from the claim text.

Method and apparatus for control of a tiered memory system

Life of this patent

Method and apparatus for control of a tiered memory system

Life of this patent

Abstract

Claims24