Method and apparatus for cache pre-fetch with offset directives

A processing system with intelligent pre-fetch comprising:

• memory for storing a pre-fetched content;
• a memory channel controller communicatively coupled to the memory and including an interface for accessing an external-source-memory;
• a processing core communicatively coupled to the memory and to the memory channel controller;
• pre-fetch controller comprising:
• pre-fetch reference register for storing a pre-fetch reference;
• stride-indicator register for storing a stride-indicator;
• transfer controller minimally capable of:
• controlling the memory channel controller to direct to the memory content from one or more locations in an external-source-memory according to a pre-fetch reference stored in the pre-fetch reference register:
• generating an additional pre-fetch reference according to the pre-fetch reference stored in the pre-fetch reference register and the stride-indicator stored in the stride-indicator register;
• and
• controlling the memory channel controller to direct to the memory content from one or more locations in an external-source-memory according to the generated additional pre-fetch reference.

A cache-memory pre-fetch controller comprising:

• control interfaces including:
• cache-tag interface for receiving cache-tag information from a cache memory and for storing cache-tag information in a cache memory;
• cache-control interface for controlling storage of information in a cache memory;
• and
• memory-channel control interface for controlling a memory channel controller;
• pre-fetch reference register for storing a pre-fetch reference;
• stride-indicator register for storing a stride-indicator;
• and
• configuration interface for receiving configuration parameters, said configuration interface being communicatively coupled to the pre-fetch reference register and the stride-indicator register;
• transfer controller minimally capable of:
• controlling the memory-channel control interface to fetch memory content from one or more external memory locations according to a pre-fetch reference stored in the pre-fetch reference register;
• controlling the cache-control interface so as to affect storage of a fetched content in a cache memory;
• generating an additional pre-fetch reference according to the pre-fetch reference stored in the pre-fetch reference register and the stride-indicator stored in the stride-indicator register;
• and
• controlling the memory channel control interface to fetch memory content from one or more external memory locations according to the generated additional pre-fetch reference.