Processor, method, and system for cache partitioning and control for accurate performance monitoring and optimization

A method comprising:

• partitioning, by cache controller circuitry, a processor cache into a plurality of cache partitions based on one or more control addresses;
• applying, by cache policy assignment circuitry, different cache policies to different subsets of the plurality of cache partitions;
• and
• tracking, by cache performance monitoring circuitry, cache events for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.

A system comprising:

• a memory;
• a processor comprising:
• a plurality of cores;
• a cache shared by the plurality of cores;
• cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses;
• cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions;
• and
• cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.