US 2019/0102300 A1 · APPARATUS AND METHOD FOR MULTI-LEVEL CACHE REQUEST TRACKING

Abstract

An apparatus and method for multi-level cache request tracking. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; a memory subsystem comprising a system memory and a multi-level cache hierarchy; a primary tracker to store a first entry associated with a memory request to transfer a cache line from the system memory or a first cache within the cache hierarchy to a second cache; primary tracker allocation circuitry to allocate and deallocate entries within the primary tracker; a secondary tracker to store a second entry associated with the memory request; secondary tracker allocation circuitry to allocate and deallocate entries within the secondary tracker; the primary tracker allocation circuitry to deallocate the first entry in response to a first indication that one or more cache coherence requirements associated with the cache line have been resolved, the secondary tracker allocation circuitry to deallocate the second entry in response to a second indication related to transmission of the cache line to the second cache.

Claims20

Dependent claims

A processor comprising:

one or more cores to execute instructions and process data;
a memory subsystem comprising a system memory and a multi-level cache hierarchy;
a primary tracker to store a first entry associated with a memory request to transfer a cache line from the system memory or a first cache within the cache hierarchy to a second cache;
primary tracker allocation circuitry to allocate and deallocate entries within the primary tracker;
a secondary tracker to store a second entry associated with the memory request;
secondary tracker allocation circuitry to allocate and deallocate entries within the secondary tracker;
the primary tracker allocation circuitry to deallocate the first entry in response to a first indication that one or more cache coherence requirements associated with the cache line have been resolved,
the secondary tracker allocation circuitry to deallocate the second entry in response to a second indication related to transmission of the cache line to the second cache.

5 more elements

Dependencies are inferred from the claim text.

Apparatus and method for multi-level cache request tracking

Life of this patent

Apparatus and method for multi-level cache request tracking

Life of this patent

Abstract

Claims20