Method and apparatus for adaptively selecting data transfer processes for single-producer-single-consumer and widely shared cache lines

A processor for managing a multi-level cache system, the processor comprising:

• a first core;
• a second core;
• a first core cache dedicated to the first core;
• a second core cache dedicated to the second core;
• a shared cache that is shared between the first core and the second core;
• and
• cache circuitry within one or more of the first core cache, the second core cache, and the shared core cache, the cache circuitry to:
• determine in response to receipt of a request for a cache line from the first core cache, whether the cache line is a widely-shared cache line or a single-producer-single-consumer cache line, and
• perform a three-hop data transfer process between the first core cache and the second core cache in response to determining that the cache line is a single-producer-single-consumer cache line,
• wherein the three-hop data transfer process transfers the cache line directly from the second core cache to the first core cache.

A non-transitory machine-readable medium containing instructions that, when performed by a processor, cause the performance of operations comprising:

• receiving, by a shared cache from a first core cache, a first request for a cache line;
• determining, by the shared cache in response to receipt of the first request, whether the cache line is a widely-shared cache line or a single-producer-single-consumer cache line;
• and
• performing, by the first core cache and a second core cache, a three-hop data transfer process in response to determining that the cache line is a single-producer-single-consumer cache line,
• wherein the three-hop data transfer process transfers the cache line directly from the second core cache to the first core cache.