COHERENT MEMORY DEVICES OVER PCIe
AssigneeIntel Corporation
InventorsIshwar Agarwal, Stephen R. Van Doren, Ramacharan Sundararaman
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Abstract
There is disclosed in an example a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space, having: a PCIe controller hub including extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space; wherein the extensions include: a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI; and a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI.
Claims25
A peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space, comprising:
- a PCIe controller hub comprising extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space;
- wherein the extensions comprise:
- a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI;
- and
- a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI.
One or more tangible, non-transitory computer-readable mediums having stored thereon instructions to provide on a host platform a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space, comprising instructions to:
- provision a PCIe controller hub comprising extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space;
- wherein the extensions comprise:
- a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI;
- and
- a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI.
A computer-implemented method of providing to a host platform a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space, comprising:
- providing PCIe controller hub services;
- providing extensions to the PCIe controller hub to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space;
- wherein providing extensions comprises:
- providing opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI;
- and
- providing scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI.
The method of claim 33, further comprising providing host-bias-to-device-bias (HBDB) flip services to enable the accelerator to flush a host cache line.
Dependencies are inferred from the claim text.