Meta Data Arrangement for Wear Leveling of Storage Class Memory

An apparatus for wear leveling control for storage class memory, the apparatus comprising:

• a cache memory;
• a nonvolatile memory comprising (D+E) nonvolatile-memory chips, wherein D nonvolatile-memory chips are configured to store input data and E nonvolatile-memory chips are configured to store extended data associated with the input data, wherein D and E are positive integers;
• a storage class memory (SCM) controller coupled to the cache memory and the nonvolatile memory;
• and
• one or more processors;
• wherein the cache memory, the nonvolatile memory, the SCM controller and said one or more processors are configured to perform at least the following:
• dividing the nonvolatile memory into memory groups;
• mapping N input group addresses corresponding a logic addresses of the memory groups to M output group addresses corresponding to physical group addresses of the memory groups using fixed mapping within a period T, wherein M and N are positive integers and M is greater than N, wherein N memory groups are used as data groups, and one or more memory groups are used as redundant groups, M is equal to a sum of N and number of the redundant groups, and wherein said mapping N input group addresses to M output group addresses causes N data groups among M memory groups to store input data in a rotated fashion;
• and
• storing Error Correction Code (ECC) check bytes and metadata associated with the data groups and the redundant groups in said E nonvolatile-memory chips, wherein the metadata corresponding to information related to said mapping N input group addresses to M output group addresses to cause N data groups among M memory groups to store the input data in a rotated fashion.