Apparatus and method for predicting a redundancy period
AssigneeArm Limited
InventorsPrakash S. RAMRAKHYANI, Jonathan Curtis BEARD
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Abstract
An apparatus comprises a plurality of memory units organised as a hierarchical memory system, wherein each of at least some of the memory units is associated with a processor element; predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.
Claims18
An apparatus comprising:
- a plurality of memory units organised as a hierarchical memory system, wherein each of at least some of said memory units is associated with a processor element;
- predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed;
- and
- an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.
An apparatus comprising:
- a plurality of means for association with a means for processing, organised as a hierarchical memory system;
- means for performing a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed;
- and
- means for selecting a selected means for processing to perform said data processing operation, wherein said selected means for processing is selected based on said predicted redundancy period.
A method for use in an apparatus comprising a plurality of memory units organised as a hierarchical memory system, wherein each of at least some of said memory units is associated with a processor element, said method comprising:
- performing a prediction process to determine a predicted redundancy period of result data of a data processing operation to performed, indicating a predicted point when said result data will be next accessed;
- and
- selecting a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.
Dependencies are inferred from the claim text.