US 2019/0102271 A1 · SEMICONDUCTOR DEVICE

Abstract

There is a need to detect faults on a path between a memory access circuit and a shared resource, faults in a logic circuit, and faults in the shared resource. A semiconductor device includes: a first memory access circuit; a second memory access circuit to check the first memory access circuit; a memory that outputs a memory address based on a first access address input from the first memory access circuit; a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit; a first address comparison circuit that compares the first access address with the memory address; and an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.

Claims17

Dependent claims

A semiconductor device comprising:

a first memory access circuit;
a second memory access circuit to check the first memory access circuit;
a memory that outputs a memory address based on a first access address input from the first memory access circuit;
a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit;
a first address comparison circuit that compares the first access address with the memory address;
and
an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.

4 more elements

A semiconductor device comprising:

a first memory access circuit;
a first memory that outputs a first memory address based on a first access address input from the first memory access circuit;
a second memory that outputs a second memory address based on a first access address input from the first memory access circuit;
a first address comparison circuit that compares the first access address with the first memory address;
a second address comparison circuit that compares the first access address with the second memory address;
and
an error control circuit that outputs a control signal based on a comparison result from the first address comparison circuit and a comparison result from the second comparison circuit.

4 more elements

A semiconductor device comprising:

a first memory access circuit including a first address generation circuit, a first address decoder to generate a first access address, a first memory selection signal, and a second memory selection signal from a first original address generated by the first address generation circuit, and a second address generation circuit to generate a high-order address of the first access address from the first memory selection signal and the second memory selection signal;
a first memory that generates a first memory address based on the first access address;
a second memory that generates a second memory address based on the first access address;
a first address comparison circuit that compares the first original address with a first restoration address resulting from combining the first memory address with a high-order address of the first access address;
a second address comparison circuit that compares the first original address with a second restoration address resulting from combining the second memory address with a high-order address of the first access address;
and
an error control circuit that outputs a control signal based on one of a comparison result from the first address comparison circuit and a comparison result from the second address comparison circuit.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims17