Back to results
US 2019/0102242 A1Published application
System and methods for hardware-software cooperative pipeline error detection
AssigneeNVIDIA Corporation
InventorsMichael Sullivan, Siva Hari, Brian Zimmer, Timothy Tsai, Stephen W. Keckler
Life of this patent
Estimating the term…
Abstract
A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.
Claims20
A method comprising:
- executing an original instruction;
- executing a duplicate instruction of the original instruction;
- generating a data portion D1 resulting from execution of the original instruction;
- generating an error correcting code portion ECC1 for the data portion D1 of the original instruction;
- generating an error correcting code portion ECC2 for a data portion D2 of the duplicate instruction;
- and
- executing logic to write-back to a register file, and to associate with one another, the data portion D1 resulting from execution of the original instruction, and the error correcting code portion ECC2 for the data portion D2 resulting from execution of the duplicate instruction.
4 more elements
A processor, comprising:
- logic to execute an original instruction and to execute a duplicate instruction of the original instruction;
- logic to generate a data portion D1 resulting from execution of the original instruction;
- logic to generate an error correcting code portion ECC1 for the data portion D1 of the original instruction;
- logic to generate an error correcting code portion ECC2 for a data portion D2 of the duplicate instruction;
- and
- logic to write-back to a register file and to associate with one another the data portion D1 resulting from execution of the original instruction and the error correcting code portion ECC2 for the data portion D2 resulting from execution of the duplicate instruction.
3 more elements
Dependencies are inferred from the claim text.