Methods and systems for executing vectorized pythagorean tuple instructions
AssigneeIntel Corporation
InventorsRoland Schulz, Jeffrey R. Hammond, Jesus Corbal
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AssigneeIntel Corporation
InventorsRoland Schulz, Jeffrey R. Hammond, Jesus Corbal
Estimating the term…
Disclosed embodiments relate generally to computer processor architecture, and, more specifically, to methods and systems for executing vectorized Pythagorean tuple instructions. In one example, a processor includes fetch circuitry to fetch an instruction having an opcode, an order, a destination identifier, and N source identifiers, N being equal to the order, and the order being one of two, three, and four, decode circuitry to decode the fetched instruction, and execution circuitry, for each element of the identified destination, to generate N squares by squaring each corresponding element of the N identified sources and generate a sum of the N squares and previous contents of the element.
A processor comprising:
The processor of clam 1, wherein the instruction further comprises a writemask, the writemask being a multi-bit value with each bit to control, for each element of the identified destination, whether the sum is stored to the element.
A method comprising:
An apparatus comprising:
A non-transitory computer-readable medium containing instructions that, when execute by a processor, cause the processor to:
Dependencies are inferred from the claim text.