System and method for merging divide and multiply-subtract operations

An apparatus comprising:

• an instruction pipeline comprising a plurality of pipeline stage circuits, and configured to process a stream of instructions in a partially parallel manner;
• wherein the plurality of pipeline stage circuits comprises:
• a first circuit configured to detect, within the instruction stream, an integer division instruction followed by a multiply-subtract instruction, wherein the integer division instruction and the multiply-subtract instruction, together, produces a remainder;
• a second circuit configured to:
• replace, within the instruction stream, the integer division instruction with a modulo instruction, and
• delete, within the instruction stream, the multiply-subtract instruction.

A method comprising:

• detecting, by a first portion of an instruction pipeline circuitry, if a division instruction followed by a subtraction instruction results in a modulo operation;
• merging, by a second portion of an instruction pipeline circuitry, the division and subtraction instructions into a merged instruction that, when executed, performs the modulo operation;
• and
• executing, by a third portion of the instruction pipeline circuitry, the merged instruction.