US 2019/0102182 A1 · APPARATUS AND METHOD FOR PERFORMING DUAL SIGNED AND UNSIGNED MULTIPLICATION OF PACKED DATA ELEMENTS

Abstract

An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to perform concurrent dual multiplications of a first packed data element from the first source register with a second packed data element from the second source register and a third packed data element from the first source register with a fourth packed data element from the second source register to generate first and second products, respectively, wherein the first and third packed data elements have a width twice as large as a width of the second and fourth packed data elements; the multiplier circuitry to select the first and third packed data elements from the first source register and the second and fourth packed data elements from the second source register in accordance with the immediate to generate the first and second products.

Claims24

Dependent claims

A processor comprising:

a decoder to decode a first instruction to generate a decoded instruction;
a first source register to store a first plurality of packed data elements;
a second source register to store a second plurality of packed data elements;
execution circuitry to execute the decoded instruction, the execution circuitry comprising:
multiplier circuitry to perform concurrent dual multiplications of a first packed data element from the first source register with a second packed data element from the second source register and a third packed data element from the first source register with a fourth packed data element from the second source register to generate first and second products, respectively, wherein the first and third packed data elements have a width twice as large as a width of the second and fourth packed data elements;
the multiplier circuitry to select the first and third packed data elements from the first source register and the second and fourth packed data elements from the second source register in accordance with the immediate to generate the first and second products;
zero-extension or sign-extension circuitry to zero-extend or sign-extend the first and second products to generate first and second results, respectively, the zero-extension or sign-extension increasing a width of the products by a specified amount;
and
a destination register to store the first and second results in specified data element positions.

6 more elements

A method comprising:

decoding a first instruction to generate a decoded instruction;
storing a first plurality of packed data elements in a first source register;
storing a second plurality of packed real and imaginary data elements in a second source register;
performing concurrent dual multiplications of a first packed data element from the first source register with a second packed data element from the second source register and a third packed data element from the first source register with a fourth packed data element from the second source register to generate first and second products, respectively, wherein the first and third packed data elements have a width twice as large as a width of the second and fourth packed data elements;
wherein the first and third packed data elements are selected from the first source register and the second and fourth packed data elements are selected from the second source register in accordance with the immediate to generate the first and second products;
zero-extending or sign-extending the first and second products to generate first and second results, respectively, the zero-extending or sign-extending increasing a width of the products by a specified amount;
and
storing the first and second results in specified data element positions in a destination register.

5 more elements

Dependencies are inferred from the claim text.

Apparatus and method for performing dual signed and unsigned multiplication of packed data elements

Life of this patent

Apparatus and method for performing dual signed and unsigned multiplication of packed data elements

Life of this patent

Abstract

Claims24