Processors and methods for privileged configuration in a spatial array

A method comprising:

• performing an operation of a dataflow graph with an interconnect network and a plurality of processing elements of a processor when an incoming operand set arrives at the plurality of processing elements, wherein the processor comprises the plurality of processing elements and the interconnect network between the plurality of processing elements, and the dataflow graph comprising a plurality of nodes is overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor according to configuration bits with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements;
• and
• configuring, with a configuration controller of the processor, the interconnect network between a first subset and a second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when a privilege bit, separate from the configuration bits, is set to a first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value.

A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

• performing an operation of a dataflow graph with an interconnect network and a plurality of processing elements of a processor when an incoming operand set arrives at the plurality of processing elements, wherein the processor comprises the plurality of processing elements and the interconnect network between the plurality of processing elements, and the dataflow graph comprising a plurality of nodes is overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor according to configuration bits with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements;
• and
• configuring, with a configuration controller of the processor, the interconnect network between a first subset and a second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when a privilege bit, separate from the configuration bits, is set to a first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value.