US 2019/0102174 A1 · APPARATUS AND METHOD FOR MULTIPLY, ADD/SUBTRACT, AND ACCUMULATE OF PACKED DATA ELEMENTS

Abstract

An apparatus and method for performing dual concurrent multiplications, subtraction/addition, and accumulation of packed data elements. For example one embodiment of a processor comprises: a decoder to decode an instruction to generate a decoded instruction; a first source register to store first and second packed data elements; a second source register to store third and fourth packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply the first and third packed data elements to generate a first temporary product and to concurrently multiply the second and fourth packed data elements to generate a second temporary product, the first through fourth packed data elements all being a first width; circuitry to negate the first temporary product to generate a negated first product; adder circuitry to add the first negated product to a first accumulated packed data element from a third source register to generate a first result, the first result being a second width which is at least twice as large as the first width; the adder circuitry to concurrently add the second temporary product to a second accumulated packed data element to generate a second result of the second width; the first and second results to be stored in specified first and second data element positions within a destination register.

Claims30

Dependent claims

A processor comprising:

a decoder to decode an instruction to generate a decoded instruction;
a first source register to store first and second packed data elements;
a second source register to store third and fourth packed data elements;
execution circuitry to execute the decoded instruction, the execution circuitry comprising:
multiplier circuitry to multiply the first and third packed data elements to generate a first temporary product and to concurrently multiply the second and fourth packed data elements to generate a second temporary product, the first through fourth packed data elements all being a first width;
circuitry to negate the first temporary product to generate a negated first product;
adder circuitry to add the first negated product to a first accumulated packed data element from a third source register to generate a first result, the first result being a second width which is at least twice as large as the first width;
the adder circuitry to concurrently add the second temporary product to a second accumulated packed data element to generate a second result of the second width;
the first and second results to be stored in specified first and second data element positions within a destination register.

6 more elements

A method comprising:

decoding an instruction to generate a decoded instruction;
storing first and second packed data elements in a first source register;
storing third and fourth packed data elements in a second source register;
multiplying the first and third packed data elements to generate a first temporary product and to concurrently multiply the second and fourth packed data elements to generate a second temporary product, the first through fourth packed data elements all being a first width;
negating the first temporary product to generate a negated first product;
adding the first negated product to a first accumulated packed data element from a third source register to generate a first result, the first result being a second width which is at least twice as large as the first width;
concurrently adding the second temporary product to a second accumulated packed data element to generate a second result of the second width;
storing the first and second results in specified first and second data element positions within a destination register.

5 more elements

A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

decoding an instruction to generate a decoded instruction;
storing first and second packed data elements in a first source register;
storing third and fourth packed data elements in a second source register;
multiplying the first and third packed data elements to generate a first temporary product and to concurrently multiply the second and fourth packed data elements to generate a second temporary product, the first through fourth packed data elements all being a first width;
negating the first temporary product to generate a negated first product;
adding the first negated product to a first accumulated packed data element from a third source register to generate a first result, the first result being a second width which is at least twice as large as the first width;
concurrently adding the second temporary product to a second accumulated packed data element to generate a second result of the second width;
storing the first and second results in specified first and second data element positions within a destination register.

5 more elements

Dependencies are inferred from the claim text.

Apparatus and method for multiply, add/subtract, and accumulate of packed data elements

Life of this patent

Apparatus and method for multiply, add/subtract, and accumulate of packed data elements

Life of this patent

Abstract

Claims30