Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
AssigneeTexas Instruments Incorporated
InventorsKenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
Life of this patent
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Abstract
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of the bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.
Claims10
A processing system comprising:
- a printed circuit board;
- a volatile memory;
- a processor on the printed circuit board for electronic computing coupled to the volatile memory and the processor including a pipeline and a set of first storage elements having a first width and a second of second storage elements having a second width, the first width being greater than the second width;
- a non-volatile memory elsewhere on the printed circuit board and coupled to the processor, for holding representations of instructions for the instruction register to save and restore the first and second sets of storage elements to the volatile memory, the instructions including a repeat instruction as well as a repeated instruction having an operand;
- said processor further including:
- an instruction operand value generating circuit operable to generate values varying in an operand value range and biasedly related to the operand of the repeated instruction represented in the non-volatile memory;
- and
- selection circuitry in the pipeline coupled to the instruction operand value generating circuit and operable to use the values to access the sets of first and second storage elements, and thereby facilitate transfers of information between the sets of first and second storage elements and the volatile memory.
An electronic debugging circuit comprising:
- a bias value generator circuit operable to supply a varying bias value in a programmable range and having a counter register;
- a pipeline register;
- an instruction circuit responsive to a first instruction to program the range of the bias value generator circuit and further responsive to a second instruction having an operand to repeatedly issue the second instruction to the pipeline register with the operand varied in an operand value range determined as a function of the varying bias value;
- and
- a scan controller having at least one scan path linking the counter register and the pipeline register to the scan controller.
A process of manufacturing comprising:
- fabricating structures on an integrated circuit wafer defining both a bias value generator circuit having a programmable range and an instruction circuit coupled to the bias value generator circuit;
- and
- electrically testing the structures to verify that the instruction circuit is responsive to a first instruction to program the range of the bias value generator circuit and that the bias value generator circuit supplies a varying bias value in the programmed range and that the instruction circuit is further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.
Dependencies are inferred from the claim text.