Scalable memory system protocol supporting programmable number of levels of indirection
AssigneeMicron Technology, Inc.
InventorJ. Thomas Pawlowski
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.
Claims20
A method, comprising:
- receiving, at a memory device, a stream of bits comprising a plurality of packets, wherein each packet comprises a levels of indirection field;
- determining a number of levels of indirection based at least in part on a combination of bits of the levels of indirection field in the stream of bits;
- and
- performing operations on memory based at least in part on the number of the levels of indirection.
A device, comprising:
- a memory system configured to:
- receive a stream of bits, wherein the stream of bits is configured to indicate a number of indirection steps based at least in part on a combination of bits of a data field in the stream of bits;
- parse addresses based at least in part on the number of indirection steps to determine a final location associated with the stream of bits;
- and
- perform operations on a memory array configured to couple to the memory system based at least in part on the final location.
A system, comprising:
- a memory device configured to receive a payload, wherein the payload comprises a levels of indirection field configured to indicate a number of levels of indirection separating a first address from a final address of a point associated with the payload;
- and
- an array configured to be accessed by the memory device in response to the memory device receiving the payload, wherein the array is accessed by the memory device based at least in part on the levels of indirection field.
Dependencies are inferred from the claim text.