Mechanism to enter or exit retention level voltage while a system-on-a-chip is in low power mode

A product comprising one or more tangible computer-readable non-transitory storage media comprising computer-executable instructions operable to, when executed by at least one computer processor, cause the at least one computer processor to implement operations at a computing platform that includes a plurality of circuitry blocks, the operations comprising:

• sending respective control signals to a Power Management Integrated Circuit (PMIC) from a first control pin and a second control pin of the computing platform;
• and
• causing the platform to transition, based on a combination of the control signals, between a low power state and a retention power state without entering an operational power state in between, causing at least part of the platform to transition including using at least one voltage pin coupled to the plurality of circuit blocks and controlled by the PMIC.

A computing platform including a plurality of circuit blocks, and further including:

• means for sending respective control signals to a Power Management Integrated Circuit (PMIC) from a first control pin and a second control pin of the computing platform;
• and
• means for causing the platform to transition, based on a combination of the control signals, between a low power state and a retention power state without entering an operational power state in between, causing at least part of the platform to transition including using at least one voltage pin coupled to the plurality of circuit blocks and controlled by the PMIC.