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US 2019/0101969 A1Published application
Control Blocks for Processor Power Management
AssigneeIntel Corporation
InventorsAlexander Gendler, Krishnakanth V. Sistla, Ankush Varma, Ariel Szapiro
Life of this patent
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Abstract
In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a power control unit;
- a master processing engine;
- a set of slave processing engines;
- and
- a voltage regulator,
- wherein the master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines.
3 more elements
A method comprising:
- receiving, by a master processing engine of a processor, a change message from a power control unit, wherein the processor comprises the master processing engine, a set of slave processing engines, and a voltage regulator;
- in response to a receipt of the change message, controlling, by the master processing engine, the voltage regulator to output a modified voltage level;
- and
- providing, by the voltage regulator, the modified voltage level to the master processing engine and the set of slave processing engines.
1 more element
A system comprising:
- a processor comprising:
- a power control unit;
- a voltage regulator;
- a set of slave processing engines;
- and
- a master processing engine to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines;
- and
- a system memory coupled to the processor.
5 more elements
Dependencies are inferred from the claim text.