Processors and methods for configurable clock gating in a spatial array

A method comprising:

• configuring, with a configuration controller of a processor, a plurality of processing elements of the processor according to configuration information for a dataflow graph, wherein the processor comprises the plurality of processing elements and an interconnect network between the plurality of processing elements, and has the dataflow graph comprising a plurality of nodes overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements;
• clock gating, with the configuration controller of the processor, at least one clocked component of a processing element based on the configuration information for the dataflow graph;
• and
• performing an operation of the dataflow graph with the interconnect network and the plurality of processing elements when an incoming operand set arrives at the plurality of processing elements.

A processor comprising:

• a plurality of processing elements;
• an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements;
• and
• a configuration controller, coupled to a first processing element and a second processing element of the plurality of processing elements and the first processing element having an output coupled to an input of the second processing element, to configure the second processing element to clock gate at least one clocked component of the second processing element, and configure the first processing element to send a reenable signal on the interconnect network to the second processing element to reenable the at least one clocked component of the second processing element when data is to be sent from the first processing element to the second processing element.

A method comprising:

• configuring, with a configuration controller of a processor coupled to a first processing element and a second processing element of a plurality of processing elements and the first processing element having an output coupled to an input of the second processing element, the second processing element to clock gate at least one clocked component of the second processing element, wherein the processor comprises the plurality of processing elements and an interconnect network between the plurality of processing elements, and has a dataflow graph comprising a plurality of nodes overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements;
• configuring, with the configuration controller, the first processing element to send a reenable signal on the interconnect network to the second processing element to reenable the at least one clocked component of the second processing element when data is to be sent from the first processing element to the second processing element;
• clock gating, with the configuration controller of the processor, the at least one clocked component of the second processing element;
• sending, with the first processing element, a reenable signal on the interconnect network to the second processing element to reenable the at least one clocked component of the second processing element when the data is sent from the first processing element to the second processing element;
• and
• performing an operation of the dataflow graph with the second processing element when an incoming operand set including the data arrives at the second processing element.