Transition scan coverage for cross clock domain logic
AssigneeSilicon Laboratories Inc.
InventorVivek Sarda
Life of this patent
Estimating the term…
Abstract
In order to increase test coverage of integrated circuits with multiple clock domains, during a capture portion of a scan test, the functional clock signals, associated with a respective one of the clock domains are synchronized to ensure back and forth capture between the faster and slower clock domain. Each of the plurality of clock signals is generated such that an active edge of each faster clock signal occurs one clock period of the faster clock signal before an active edge of each slower clock signal.
Claims20
A method for testing a device with multiple clock domains, comprising:
- generating a first clock signal having a first clock signal first active edge occurring at a first time relative to deassertion of a scan enable signal and having a first clock signal second rising edge occurring at a second time;
- generating a second clock signal having a second clock signal first active edge occurring one clock signal period before the second time;
- and
- generating a third clock signal having a third clock signal first active edge occurring at the second time.
An integrated circuit comprising:
- a plurality of on-chip clock control circuits coupled to receive an input clock signal and to generate a plurality of clock signals having different frequencies during a capture portion of a scan test;
- and
- wherein an active edge of each faster clock signal of the plurality of clock signals, occurs one clock cycle of each faster clock signal before an active edge of each slower clock signal.
A method for testing a device with multiple clock domains, comprising:
- generating a plurality of clock signals, during a capture portion of a scan test, each of the plurality of clock signals associated with a respective one of a plurality of clock domains;
- and
- generating each of the plurality of clock signals such that an active edge of each faster clock signal of the plurality of clock signals occurs one clock period of each faster clock signal before an active edge of each slower clock signal of the plurality of clock signals.
Dependencies are inferred from the claim text.