US 2019/0101585 A1 · EVALUATING A GATE-SOURCE LEAKAGE CURRENT IN A TRANSISTOR DEVICE

Abstract

Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.

Claims18

Dependent claims

A method, comprising:

discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor being connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging;
discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor being connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging;
comparing a ratio between the first discharging time and the second discharging time with a predefined threshold;
and
detecting a fault based on the comparing.

2 more elements

A circuit arrangement, comprising:

a transistor device with a gate node, a source node, a gate-source capacitance and between the gate node and the source node, and a gate-source resistance between the gate node and the source node;
an electronic circuit connected between the gate node and the source node and comprising a control circuit, a first resistor connected between the gate node and the source node, and a second resistor,
wherein the control circuit is configured,
in a first test cycle, to measure a first discharging time associated with discharging the gate-source capacitance from a first voltage level to a second voltage level,
in a second test cycle, to connect the second resistor between the gate node and the source node and measure a second discharging time associated with discharging the gate-source capacitance from the first voltage level to the second voltage level,
to compare a ratio between the first discharging time and the second discharging time with a predefined threshold, and
to detect a fault based on the comparing.

4 more elements

Dependencies are inferred from the claim text.

Evaluating a gate-source leakage current in a transistor device

Life of this patent

Evaluating a gate-source leakage current in a transistor device

Life of this patent

Abstract

Claims18