Memory decision feedback equalizer testing
AssigneeMicron Technology, Inc.
InventorsRaghukiran Sreeramaneni, Jennifer E. Taylor, Liang Liu
Life of this patent
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Abstract
A device includes one or more memory banks configured to store data. The device also includes a data receiver configured to receive distorted input data as part of a data stream, apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, and generate the data by applying the correction factor to the distorted data. The device further includes a test circuit internal to the device, wherein the test circuit is configured to generate the data stream.
Claims34
A memory device, comprising:
- one or more memory banks configured to store data;
- a data receiver configured to:
- receive distorted input data as part of a data stream;
- apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data;
- and
- generate the data by applying the correction factor to the distorted data;
- and
- a test circuit internal to the memory device, wherein the test circuit is configured to generate the data stream.
A semiconductor device, comprising:
- a test circuit internal to the device, wherein the test circuit is configured to:
- generate a data stream comprising a data value;
- and
- generate a control signal;
- a data transmitter configured to alter a characteristic of the data value of the data stream based upon the control signal;
- and
- a data receiver configured to receive the data value having an altered characteristic and apply an inverse value of the altered characteristic to the data value to regenerate the data value.
A method, comprising:
- placing a semiconductor device into a testing mode of operation;
- internally generating a data stream comprising a data value in the semiconductor device;
- internally generating a control signal configured to activate transmission legs of a transmitter at a particular strength in the semiconductor device;
- transmitting the data value from at least one activated transmission leg as an input data signal;
- and
- applying decision feedback equalization to the input data signal to correct for inter-symbol interference distortion of the input data signal to generate an equalized data value.
A memory testing device, comprising:
- a processor configured to:
- receive an indication of tap values to be applied by decision feedback circuitry of a memory device;
- and
- generate a modified data stream to mimic inter-symbol interference of a data stream correctable by the tap values;
- and
- an output configured to transmit the modified data stream as an input data stream to the memory device.
A tangible non-transitory computer-readable medium having computer executable code stored thereon, the code comprising instructions to cause a processor to:
- generate a data stream;
- transmit the data stream to a semiconductor device;
- receive a first output data stream from the semiconductor device, wherein the first output data stream comprises a decision feedback equalized data stream of the input data stream;
- generate a modified data stream to mimic inter-symbol interference of the data stream correctable by decision feedback equalization circuitry of the memory device;
- and
- receive a second output data stream from the semiconductor device, wherein the second output data stream comprises a decision feedback equalized data stream of the modified data stream.
Dependencies are inferred from the claim text.