Multi-Rate Transceiver Circuitry

A method, comprising:

• detecting a change in frequency of a reference clock signal received from external circuitry from a first frequency to a second frequency;
• and
• in response to detecting the change in frequency of the reference clock signal:
• reconfiguring phase-locked loop (PLL) circuitry to generate a receiver clock signal for receiver circuitry based at least in part on the change in frequency of the reference clock signal;
• and
• reconfiguring the receiver circuitry based at least in part on the change in frequency of the reference clock signal.

Circuitry, comprising:

• detector circuitry configured to receive a reference clock signal from external circuitry and to detect a change in frequency of the reference clock signal from a first frequency to a second frequency;
• and
• control circuitry configured to, in response to the detector circuitry detecting the change in frequency of the reference clock signal:
• reconfigure phase-locked loop circuitry configured to generate a receiver clock signal based at least in part on the change in frequency of the reference clock signal;
• and
• reconfigure receiver circuitry to operate based at least in part on the receiver clock signal.

Circuitry, comprising:

• detector circuitry configured to receive a reference clock signal from external circuitry and to detect a change in frequency of the reference clock signal from a first frequency to a second frequency;
• and
• control circuitry configured to, in response to the detector circuitry detecting the change in the frequency of the reference clock signal:
• reconfigure clock generating circuitry configured to generate a transmitter clock signal based at least in part on the change in frequency of the reference clock signal;
• and
• reconfigure transmitter circuitry based at least in part on the change in the frequency of the reference clock signal.