Memory system decoding design and operating method thereof
AssigneeSK hynix Inc.
InventorsChenrong XIONG, Fan ZHANG, Yu CAI, Aman BHATIA, Naveen KUMAR
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Abstract
A semiconductor memory system and an operating method thereof include a plurality of memory devices; and a controller coupled with the memory devices and configured to perform a decoding process to collect at least an output vector associated with an input bit vector, wherein the input bit vector corresponds to a plurality of variable nodes; divide the plurality of variable nodes into a plurality of groups; calculate syndrome of the output vector; and update flipping threshold and flipping indicator of each of the plurality of variable nodes.
Claims20
A semiconductor memory system comprising:
- a plurality of memory devices;
- and
- a controller coupled with the memory devices and configured to perform a decoding process to
- collect at least an output vector associated with an input bit vector, wherein the input bit vector corresponds to a plurality of variable nodes;
- divide the plurality of variable nodes into a plurality of groups;
- calculate syndrome of the output vector;
- and
- update flipping threshold and flipping indicator of each of the plurality of variable nodes.
An operating method of a semiconductor memory system comprising:
- performing a decoding process including
- collecting at least an output vector associated with an input bit vector, wherein the input bit vector corresponds to a plurality of variable nodes;
- dividing the plurality of variable nodes into a plurality of groups;
- calculating syndrome of the output vector;
- and
- updating flipping threshold and flipping indicator of each of the plurality of variable nodes.
Dependencies are inferred from the claim text.