Clock generation circuit and clock signal generation method

A clock signal generation method, wherein the method is applied to a clock generation circuit, the clock generation circuit comprises a first clock source, a second clock source, and a logic gate circuit, and wherein the first clock source comprises a first oscillation circuit and a first direct current bias circuit;

• and the method comprises:
• generating, by the first oscillation circuit, a first clock signal;
• sending, by the first oscillation circuit, the first clock signal to the first direct current bias circuit;
• removing, by the first direct current bias circuit, a direct current component from the first clock signal, and superimposing a first direct current voltage on the first clock signal obtained after the direct current component is removed, to generate a second clock signal, wherein a voltage value of the first direct current voltage is greater than a high-level decision threshold of the logic gate circuit, and the voltage value of the first direct current voltage is less than a difference between a low-level decision threshold of the logic gate circuit and a low-level voltage value of the first clock signal;
• generating, by the second clock source, a third clock signal, wherein a difference between frequencies of the third clock signal and the second clock signal is less than a first preset value;
• and
• receiving, by the logic gate circuit, the second clock signal and the third clock signal, and performing an AND logical operation on the second clock signal and the third clock signal to generate a fourth clock signal.

A clock generation circuit, comprising a first clock source, a second clock source, and a logic gate circuit, wherein the first clock source is coupled to the logic gate circuit and the second clock source is coupled to the logic gate circuit, wherein the first clock source comprises a first oscillation circuit and a first direct current bias circuit, the first oscillation circuit is coupled to the first direct current bias circuit, and the first direct current bias circuit is coupled to the logic gate circuit, wherein

• the first oscillation circuit is configured to generate a first clock signal;
• the first direct current bias circuit is configured to:
• remove a direct current component from the first clock signal, and superimpose a first direct current voltage on the first clock signal obtained after the direct current component is removed, to generate a second clock signal, wherein a voltage value of the first direct current voltage is less than a low-level decision threshold of the logic gate circuit, and the voltage value of the first direct current voltage is greater than a difference between a high-level decision threshold of the logic gate circuit and a high-level voltage value of the first clock signal;
• the second clock source is configured to generate a third clock signal, wherein an absolute value of a difference between a frequency of the third clock signal and a frequency of the second clock signal is less than a first preset value;
• and
• the logic gate circuit is configured to:
• receive the second clock signal and the third clock signal, and perform an OR logical operation on the second clock signal and the third clock signal to generate a fourth clock signal.