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US 2019/0097640 A1Published application
Phase-locked loop output adjustment
AssigneeQUALCOMM Incorporated
InventorsKarthik Nagarajan, Chenling Huang, Debesh Bhatta
Life of this patent
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Abstract
A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
Claims30
An apparatus comprising:
- a phase locked loop (PLL) circuit;
- a time difference circuit coupled to an input of the PLL circuit and an output of the PLL circuit;
- a time to voltage conversion circuit coupled to an output of the time difference circuit;
- and
- a voltage controlled delay line coupled to the output of the PLL circuit and an output of the time to voltage conversion circuit.
2 more elements
A method comprising:
- comparing an edge of a first clock signal with an edge of an output signal from a phase locked loop to detect a time difference between the edge of the first clock signal and the edge of the output signal;
- converting the time difference to a voltage change;
- and
- controlling an amount of time delay on the output signal of the phase locked loop based on the voltage change.
1 more element
An apparatus comprising:
- means for comparing an edge of a first clock signal with an edge of a phase-locked loop output signal and outputting a time difference between the edges;
- means for converting the time difference into a change in a voltage signal, wherein the change in the voltage signal is proportional to the time difference;
- and
- means for delaying the phase-locked loop output signal based on the change in the voltage signal.
1 more element
An apparatus comprising:
- a phase-locked loop;
- a delta-T to delta-V circuit having inputs coupled to an input and an output of the phase-locked loop;
- and
- a delta-V to delta-T circuit having inputs coupled to the output of the phase-locked loop and an output of the delta-T to delta-V circuit.
1 more element
Dependencies are inferred from the claim text.