Fast locking clock and data recovery circuit
AssigneeSynopsys, Inc.
InventorsBiman Chattopadhyay, Ravi Mehta
Life of this patent
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Abstract
A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.
Claims15
A clock and data recovery (CDR) circuit, comprising:
- a phase detector that receives serialized data and a voltage controlled oscillator (VCO) clock signal, determines that the VCO clock signal is at least one of early and late with respect to the serialized data, and generates an early-late signal;
- a VCO that receives the early-late signal and a frequency control code, and generates the VCO clock signal, wherein the VCO controls a phase of the VCO clock signal based on the early-late signal, and wherein the VCO controls a frequency of the VCO clock signal based on the frequency control code;
- a frequency control circuit that receives the VCO clock signal and a reference clock signal, and generates an up/down signal;
- and
- a first counter that receives the up/down signal and outputs the frequency control code, wherein the first counter performs at least one of incrementing and decrementing the frequency control code by a predefined value based on the up/down signal for matching the frequency of the VCO clock signal to a target frequency.
A clock and data recovery (CDR) circuit, comprising:
- a phase detector that receives serialized data and a voltage controlled oscillator (VCO) clock signal, determines that the VCO clock signal is at least one of early and late with respect to the serialized data, and generates an early-late signal;
- a VCO that receives the early-late signal and a frequency control code, and generates the VCO clock signal, wherein the VCO controls a phase of the VCO clock signal based on the early-late signal, and wherein the VCO controls a frequency of the VCO clock signal based on the frequency control code;
- a frequency control circuit comprising:
- a first counter that receives the VCO clock signal, counts a number of clock cycles of the VCO clock signal over a predetermined time period, and generates a clock count value;
- and
- a digital comparator that receives the clock count value and a reference clock signal, compares the clock count value with a target count value, and generates an up/down signal;
- and
- a second counter that receives an up/down signal and outputs the frequency control code, wherein the first counter performs at least one of incrementing and decrementing the frequency control code by a predefined value based on the up/down signal for matching the frequency of the VCO clock signal to a target frequency.
Dependencies are inferred from the claim text.