Jitter reduction in clock and data recovery circuits
AssigneeApple Inc.
InventorsWenbo Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari
Life of this patent
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Abstract
Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
Claims21
An apparatus, comprising:
- a slicing circuit configured to sample an input signal to generate:
- a first sampled data signal based on a first clock signal, and
- a second sampled data signal based on a second clock signal;
- a phase detector circuit configured to:
- perform a comparison of a phase of the first sampled data signal to a phase of the second sampled data signal;
- and
- generate, based on a result of the comparison, a first control signal and a second control signal that are indicative of a difference in phase between the first sampled data signal and the second sampled data signal;
- a control circuit configured to generate a third control signal and a fourth control signal using the first and second control signals;
- a first charge pump circuit configured to supply a first current to a circuit node using the first and second control signals generated by the phase detector circuit;
- a second charge pump circuit configured to supply a second current to the circuit node based on the third and fourth control signals, wherein the second current is of opposite polarity to the first current;
- and
- a voltage-controlled oscillator circuit configured to adjust a frequency of the first and second clock signals based on a voltage of the circuit node.
A method, comprising:
- generating, by a voltage-controlled oscillator, a first clock signal and a second clock signal based on a voltage of a circuit node;
- sampling, by a slicing circuit, an input signal using the first clock signal and the second clock signal to generate a first sampled data signal and a second sampled data signal, respectively;
- comparing, by a phase detector circuit, a phase of the first sampled data signal and a phase of the second sampled data signal;
- generating, by the phase detector circuit based on a result of the comparing, first and second control signals that are indicative of a difference in phase between the first sampled data signal and the second sampled data signal;
- generating, by a control circuit, third and fourth control signals using the first and second control signals;
- modifying, by a first charge pump, a voltage of a circuit node, including by:
- generating a first current using the first and second control signals generated by the phase detector circuit;
- modifying, by a second charge pump, the voltage of the circuit node, including by:
- generating a second current based on the third and fourth control signals, wherein the second current is of opposite polarity to the first current;
- and
- adjusting, by the voltage-controlled oscillator, a frequency of the first clock signal and the second block signal based on the voltage of the circuit node.
A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the hardware integrated circuit according to the design, wherein the design information specifies that the hardware integrated circuit comprises:
- a slicing circuit configured to sample an input signal to generate:
- a first sampled data signal based on a first clock signal, and
- a second sampled data signal based on a second clock signal;
- a phase detector circuit configured to:
- perform a comparison of a phase of the first sampled data signal and a phase of the second sampled data signal;
- and
- generate a first control signal and a second control signal based on a result of the comparison;
- a control circuit configured to generate a third and a fourth control signal using latched versions of the first and second control signals;
- a first charge pump circuit configured to supply a first current to a circuit node based on the first and second control signals;
- a second charge pump circuit configured to supply a second current to the circuit node based on the third and fourth control signals, wherein the second current is of opposite polarity to the first current;
- and
- a voltage-controlled oscillator circuit configured to adjust a frequency of the first and second clock signals based on a voltage of the circuit node.
(canceled)
Dependencies are inferred from the claim text.