Clock synthesis for frequency scaling in programmable logic designs

A method comprising:

• receiving in a controller an instruction to change a frequency of an output clock signal provided by a configurable clock from an initial clock frequency to a final clock frequency, wherein a configurable clock generator comprises a first clock signal generator that generates a first internal clock signal at the initial clock frequency, and wherein the configurable clock provides the first internal clock signal as the output clock signal;
• reconfiguring a second clock signal generator of a configurable clock to provide a second internal clock signal at a first incremental frequency;
• providing the second internal clock signal as the output clock signal of the configurable clock;
• reconfiguring the first clock signal generator of the configurable clock to provide the first internal clock signal at a second incremental frequency;
• and
• providing the first clock signal as the output signal of the configurable clock,
• wherein a difference between the first incremental frequency, and the second incremental frequency comprises an incremental difference.

Clock generating circuitry, comprising:

• first clock signal generating circuitry that provides a first internal clock signal;
• second clock signal generating circuitry that provides a second internal clock signal;
• clock selection circuitry that receives the first internal clock signal, the second internal clock signal;
• and
• control circuitry configured to:
• adjust a frequency of the first internal clock signal;
• adjust a frequency of second internal clock signal;
• and
• configure the clock selection circuitry to provide the first internal clock signal or the second internal clock signal as an output clock signal of the clock generating circuitry.