Synchronizing a self-timed processor with an external event

A self-timed processor comprising:

• trigger logic having:
• a trigger input to receive an event trigger signal, a data input set to a data value of 1, a trigger output to send a trigger output signal when the event trigger signal is received, and a reset input to reset the trigger output signal;
• a delay insensitive asynchronous logic (DIAL) block having:
• multi-rail DIAL inputs to receive at least a first multi-rail DIAL input data signal having a) a first rail input that is the trigger output signal, and b) a second rail input that is set to a data value of 0;
• multi-rail DIAL to process at least the first multi-rail DIAL input data signal using multi-rail DIAL data process values;
• and
• data phase completion logic to output a completion signal indicating an end of a data propagate phase of the DIAL block to reset the trigger output signal when the multi-rail data DIAL data process values reach a DIAL valid state.