High-voltage level-shifter circuitry

A voltage level-shifter circuit comprising:

• low-voltage domain circuitry configured to generate voltage input signals with reference to a low-voltage domain ground node;
• high-voltage domain circuitry capacitively coupled to the low-voltage domain circuitry and configured to generate voltage output signals, with reference to a high-voltage domain common node, that correspond to a level-shifted version of the voltage input signals;
• wherein the high-voltage domain circuitry comprises charge amplifier circuitry, latch circuitry, and feedback circuitry,
• wherein the charge amplifier circuitry is configured to receive as input the voltage input signals and to drive the latch circuitry to generate the voltage output signals,
• wherein the feedback circuitry is configured to generate a slope detection signal in response to an erroneous condition at the latch circuitry, and
• wherein the voltage level-shifter circuit further comprises common mode rejection circuitry configured to suppress propagation of a common mode error signal to the latch circuitry, wherein the common mode rejection circuitry comprises first clamp circuitry coupled to a control terminal of a first transistor of the charge amplifier circuitry and configured to pull the control terminal of the first transistor to a voltage potential of the high-voltage domain common node in response to the slope detection signal, and second clamp circuitry coupled to a control terminal of a second transistor of the charge amplifier circuitry and configured to pull the control terminal of the second transistor to the voltage potential of the high-voltage domain common node in response to the slope detection signal.

A voltage level-shifter circuit comprising:

• low-voltage domain circuitry configured to generate voltage input signals with reference to a low-voltage domain ground node;
• high-voltage domain circuitry capacitively coupled to the low-voltage domain circuitry and configured to generate voltage output signals, with reference to a high-voltage domain common node, that correspond to a level-shifted version of the voltage input signals;
• wherein the high-voltage domain circuitry comprises charge amplifier circuitry and latch circuitry,
• wherein the charge amplifier circuitry is configured to receive as input the voltage input signals and to drive the latch circuitry to generate the voltage output signals;
• and
• wherein the voltage level-shifter circuit further comprises bit-mismatch corrective circuitry configured to enforce the voltage output signals to a value that corresponds to the level-shifted version of the voltage input signals, wherein the bit-mismatch corrective circuitry comprises:
• sampling circuitry configured to sample the voltage output signals;
• clock circuitry configured to control the sampling circuit to sample the voltage output signals at a particular rate;
• and
• comparator circuitry configured to compare an instant logic level of the voltage input signals with a sampled logic level of the voltage output signals, and to output a bit-correction signal to the low-voltage domain circuitry that is coupled into the high-voltage domain circuitry to enforce the voltage output signals to the value that corresponds to the level-shifted version of the voltage input signals.

A voltage level-shifter circuit comprising:

• low-voltage domain circuitry configured to generate voltage input signals with reference to a low-voltage domain ground node;
• high-voltage domain circuitry capacitively coupled to the low-voltage domain circuitry and configured to generate voltage output signals, with reference to a high-voltage domain common node, that correspond to a level-shifted version of the voltage input signals;
• wherein the high-voltage domain circuitry comprises charge amplifier circuitry and latch circuitry,
• wherein the charge amplifier circuitry is configured to receive as input the voltage input signals and to drive the latch circuitry to generate the voltage output signals;
• and
• wherein the voltage level-shifter circuit further comprises phase correction circuitry configured to dampen oscillations at nodes of the latch circuitry, wherein the phase correction circuitry comprises a resistor-capacitor network coupled between an output of the latch circuitry and inputs of the overvoltage protection circuitry.

A method comprising:

• receiving, by charge amplifier circuitry of a voltage level-shifter circuit, an input bit from low-voltage domain circuitry of the voltage level-shifter circuit and, in response, driving latch circuitry of the voltage level-shifter circuit to store an output bit that is a level-shifted version of the input bit;
• generating, by feedback circuitry of the voltage level shifter circuit, a slope detection signal in response to an erroneous condition at the latch circuitry;
• and
• suppressing, by common mode rejection circuitry of the voltage level-shifter circuit, propagation of a common mode error signal to the latch circuitry, wherein the common mode rejection circuitry comprises first clamp circuitry coupled to a control terminal of a first transistor of the charge amplifier circuitry and configured to pull the control terminal of the first transistor to a voltage potential of a high-voltage domain common node in response to the slope detection signal, and second clamp circuitry coupled to a control terminal of a second transistor of the charge amplifier circuitry and configured to pull the control terminal of the second transistor to the voltage potential of the high-voltage domain common node in response to the slope detection signal.