Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times

An apparatus, comprising:

• a clock generator circuit comprising a two-phase flip-flop circuit configured to provide an output signal, wherein the two-phase flip-flop circuit comprises a two-phase flip-flop and a driver circuit, wherein the two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal, wherein the first driver control signal and the second driver control signal are complementary, wherein the driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal, wherein the two-phase flip-flop comprises:
• a master latch configured to receive an input signal and to latch a first signal at a first node in response to the clock signal and latch a second signal at a second node in response to the clock signal, wherein the master latch comprises a clocked inverter coupled to a NAND gate, wherein the clocked inverter is configured to provide the input signal to the NAND gate responsive to the clock signal;
• wherein the NAND gate is configured to receive a reset signal and is configured to provide an output to the first node responsive to the reset signal and the output of the inverter;
• a first slave latch configured to latch the first signal at a third node in response to the clock signal, wherein the first driver control signal is provided from the third node;
• and
• a second slave latch configured to latch the second signal at a fourth node in response to the clock signal, wherein the second driver control signal is provided from the fourth node.