Low Noise Charge Pump Method and Apparatus

A charge pump clock generating circuit configured to generate a clock signal for a capacitive charge pump comprising at least one transfer capacitor having an input terminal and an output terminal, and a plurality of transfer capacitor coupling switches, each coupled to the clock signal and to one of the input terminal or output terminal of a corresponding one of the at least one transfer capacitor, each transfer capacitor coupling switch being switchable between a conducting state and a non-conducting state under control of the coupled clock signal, the charge pump clock generating circuit including:

• (a) a ring oscillator comprising an odd number of inverting driver sections cascaded sequentially in a ring such that each driver section has an output coupled to a next driver section input, wherein a first driver section is next after a last driver section and the output of the last driver section constitutes the clock signal;
• and
• (b) active limiting circuitry associated with each driver section, the active limiting circuitry including a source current limit circuit coupled between a voltage source and the associated driver section and configured to limit the current source capability of the associated driver section, and a sink current limit circuit coupled between the associated driver section and a common reference voltage and configured to limit the current sink capability of the associated driver section, wherein the active limiting circuitry limits output transitions dv/dt of the clock signal and causes the clock signal to have a substantially sine-like shape;
• wherein the plurality of transfer capacitor coupling switches are controlled by the coupled clock signal so as to couple the input terminal of the corresponding transfer capacitor to a voltage source during periodic first times, and to couple the output terminal of the corresponding transfer capacitor to a voltage output terminal during periodic second times that are not concurrent with the periodic first times, and
• wherein there are periods of time when all transfer capacitor coupling switches coupled to a corresponding transfer capacitor are in the non-conducting state.

A charge pump circuit for generating an output voltage supply, comprising:

• (a) a charge pump clock generating circuit generating a clock signal, the charge pump clock generating circuit including a ring oscillator comprising an odd number of inverting driver sections cascaded sequentially in a ring such that each driver section has an output coupled to a next driver section input, wherein a first driver section is next after a last driver section and the output of the last driver section constitutes the clock signal, and wherein each driver section includes associated active limiting circuitry, the active limiting circuitry including a source current limit circuit coupled between a voltage source and the associated driver section and configured to limit the current source capability of the associated driver section, and a sink current limit circuit coupled between the associated driver section and a common reference voltage and configured to limit the current sink capability of the associated driver section, wherein the active limiting circuitry limits output transitions dv/dt of the clock signal and causes the clock signal to have a substantially sine-like shape;
• and
• (b) a capacitive charge pump comprising at least one transfer capacitor having an input terminal and an output terminal, and a plurality of transfer capacitor coupling switches, each coupled to the clock signal and to one of the input terminal or output terminal of a corresponding one of the at least one transfer capacitor, and each switchable between a conducting state and a non-conducting state under control of the coupled clock signal;
• wherein the plurality of transfer capacitor coupling switches are controlled by the coupled clock signal so as to couple the input terminal of the corresponding transfer capacitor to a voltage source during periodic first times, and to couple the output terminal of the corresponding transfer capacitor to a voltage output terminal during periodic second times that are not concurrent with the periodic first times, and
• wherein there are periods of time when all transfer capacitor coupling switches coupled to a corresponding transfer capacitor are in the non-conducting state.

A charge pump circuit for generating a low noise output voltage supply, comprising:

• (a) a charge pump clock generating circuit generating a clock signal, the charge pump clock generating circuit including a ring oscillator comprising an odd number of inverting driver sections cascaded sequentially in a ring such that each driver section has an output coupled to a next driver section input, wherein a first driver section is next after a last driver section and the output of the last driver section constitutes the clock signal, and wherein each driver section includes associated active limiting circuitry, the active limiting circuitry including a source current limit circuit coupled between a voltage source and the associated driver section and configured to limit the current source capability of the associated driver section, and a sink current limit circuit coupled between the associated driver section and a common reference voltage and configured to limit the current sink capability of the associated driver section, wherein the active limiting circuitry limits output transitions dv/dt of the clock signal and causes the clock signal to have a substantially sine-like shape;
• (b) a capacitive charge pump comprising at least one transfer capacitor having an input terminal and an output terminal, and a plurality of transfer capacitor coupling switches, each coupled to the clock signal and to one of the input terminal or output terminal of a corresponding one of the at least one transfer capacitor, and each switchable between a conducting state and a non-conducting state under control of the coupled clock signal, the plurality of transfer capacitor coupling switches including at least:
• (1) a first transfer capacitor coupling switch coupled between the input terminal of the corresponding transfer capacitor and a voltage source;
• (2) a second transfer capacitor coupling switch coupled between the input terminal of the corresponding transfer capacitor and a common reference;
• (3) a third transfer capacitor coupling switch coupled between the output terminal of the corresponding transfer capacitor and a voltage output terminal;
• and
• (4) a fourth transfer capacitor coupling switch coupled between the output terminal of the corresponding transfer capacitor and the common reference;
• wherein the plurality of transfer capacitor coupling switches are controlled by the coupled clock signal so as to couple the input terminal of the corresponding transfer capacitor to a voltage source during periodic first times, and to couple the output terminal of the corresponding transfer capacitor to a voltage output terminal during periodic second times that are not concurrent with the periodic first times, and
• wherein there are periods of time when all transfer capacitor coupling switches coupled to a corresponding transfer capacitor are in the non-conducting state.