Vertical thin film transistor

A semiconductor device, comprising:

• a substrate having front end of the line (FEOL) devices formed thereon;
• a cross bar grid including first lines and second lines formed transversely to the first lines;
• back end of the line (BEOL) vertical transistors formed over an interlevel dielectric layer, the vertical transistors each including:
• a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer, the drain layer formed from a polycrystalline material;
• a gate electrode formed in a common plane with the channel layer;
• a gate dielectric formed vertically between the gate electrode and the channel layer;
• a first contact connecting the source layer to a first line of the first lines;
• a second contact formed on an opposite side vertically from the first contact and connecting the drain layer to a second line of the second lines;
• and
• a barrier metal layer interfacing between the polycrystalline material of the drain layer and the second contact.

A method for forming a semiconductor device, comprising:

• forming a first contact through an interlevel dielectric layer (ILD);
• forming a stack of layers on the ILD layer and over the first contact, the stack of layers including a source layer, a drain layer and a channel layer between the source layer and the drain layer;
• forming a spacer layer over the ILD layer;
• conformally depositing a gate dielectric over the spacer layer and the stack of layers;
• forming a gate electrode in a common plane with the channel layer over the gate dielectric on the spacer layer;
• and
• forming a second contact on an opposite side vertically from the first contact.