Compact Vertical Injection Punch through Floating Gate Analog Memory and a Manufacture Thereof

A neural network, comprising:

• a vertical injection punchthrough-based metal oxide semiconductor (VIPMOS) device, the device including:
• a control gate;
• an erase gate;
• a floating gate;
• and
• an active area including an injector and a drain;
• wherein the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the active area, and
• wherein the injector and the drain are located on a same isolation island that is separate from a different isolation island which includes the control gate, the erase gate, and the floating gate.

A floating gate manufacturing method, the method comprising:

• growing a P+ EPI on an etched P-region;
• implanting an n-layer on an etched N+ region;
• growing an N+ EPI layer on the implanted n-layer in the etched N+ region;
• and
• making contacts to a control gate, an erase gate, and a floating gate,
• wherein the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the N+ region and the P-region.